Importance

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Abstract

Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.

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First Claim