Accelerating data packet parsing

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United States of America Patent

PATENT NO 8854996
SERIAL NO

13183953

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Abstract

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Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Abel, Francois Rueschlikon, CH 29 302
Calvignac, Jean L Raleigh, US 70 1441
Chang, Chih-jen Apex, US 84 1038
Damon, Philippe Chapel Hill, US 51 954
Verplanken, Fabrice J LaGaude, FR 45 553

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