System and method for high performance synchronous DRAM memory controller
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United States of America Patent
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Oct 7, 2014
Grant Date -
Jun 17, 2010
app pub date -
Dec 16, 2008
filing date -
Dec 16, 2008
priority date (Note) -
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Abstract
The disclosed system and method enhances performance of pipelined data transactions involving FIFO buffers by implementing a transaction length indicator in a transaction header. The length indicator in the header is formed by components coupled to a memory controller through FIFO buffers. The memory controller uses the length indicator to execute pipelined data transfers at relatively high speeds without causing additional inadvertent shifts or indexes in the FIFO buffer being read. The system and method can be applied to any memory type in general, and avoids the use of additional control signals or added complexity or size in the memory controller.
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