Memory control apparatus and memory control method for controlling the priority of memory accesses
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United States of America Patent
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Oct 7, 2014
Grant Date -
Mar 22, 2012
app pub date -
Sep 2, 2011
filing date -
Sep 17, 2010
priority date (Note) -
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Abstract
Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory control apparatus, which is connected with a plurality of masters and a plurality of memories having a power saving mode, arbitrates memory accesses from the plurality of the masters, monitors whether each of the plurality of the memories is in the power saving state, and determines the priorities of the memory accesses according to the result of the detection of the power saving mode.
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