Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures

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United States of America Patent

PATENT NO 8856546
APP PUB NO 20130332742A1
SERIAL NO

13490931

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Abstract

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A processing apparatus may comprise logic to preprocess a message according to a selected secure hash algorithm (SHA) algorithm to generate a plurality of message blocks, logic to generate hash values by preparing message schedules in parallel using single instruction multiple data (SIMD) instructions for the plurality of message blocks and to perform compression in serial for the plurality of message blocks, and logic to generate a message digest conforming to the selected SHA algorithm.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gueron, Shay Haifa, IL 146 2221
Krasnov, Vlad Nesher, Z, IL 30 568

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