Congestion estimation based on routing resources of programmable logic devices
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United States of America Patent
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Oct 7, 2014
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app pub date -
Dec 17, 2008
filing date -
Dec 17, 2008
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Abstract
A computer-implemented method of estimating signal congestion in routing resources of a programmable logic device (PLD), wherein the routing resources include configurable interface blocks (CIBs) and wires of different types supported by the CIBs. The method includes identifying, from a representation of a PLD stored within a computer system, components of the PLD to be connected in a configuration of the PLD. A CIB associated with an identified PLD component is then selected. A wire type supported by the selected CIB is also selected. The number of wires of the selected type needed at the selected CIB to implement the PLD configuration and the number of wires of the selected type provided by the CIB are calculated. Signal congestion at the selected CIB is estimated from at least the needed number of wires and the provided number of wires.
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