Test coverage of integrated circuits with masking pattern selection

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United States of America Patent

PATENT NO 8856720
APP PUB NO 20140189612A1
SERIAL NO

13733248

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Abstract

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A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Douskey, Steven M Rochester, US 63 258
Fitch, Ryan A Southfield, US 19 69
Hamilton, Michael J Rochester, US 32 88
Kaufer, Amanda R Rochester, US 31 85

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