Multi-level charge storage transistors and associated methods
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United States of America Patent
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Oct 14, 2014
Grant Date -
May 23, 2013
app pub date -
Jan 18, 2013
filing date -
Apr 9, 2010
priority date (Note) -
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Abstract
Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.
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