Integrated circuit fabrication
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United States of America Patent
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Oct 14, 2014
Issued Date -
N/A
app pub date -
Aug 8, 2013
filing date -
Mar 28, 2005
priority date (Note) -
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Abstract
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
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