Semiconductor storage device and data control method thereof
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United States of America Patent
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Oct 14, 2014
Grant Date -
Sep 5, 2013
app pub date -
Aug 29, 2012
filing date -
Sep 22, 2011
priority date (Note) -
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Abstract
In a memory cell array, memory cells each including a variable resistance element are arranged at crossing portions between a plurality of first wiring and a plurality of second wirings. A control circuit executes a set operation, a reset operation, and a training operation. In the set operation, a set pulse is applied to the variable resistance element to change the variable resistance element from a high resistance state to a low resistance state. In the reset operation, a reset pulse having an opposite polarity to the polarity of the set pulse is applied to the variable resistance element to change the variable resistance element from the low resistance state to the high resistance state. In the training operation, the set pulse and the reset pulse are continuously applied to the variable resistance element.
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