Processor architecture verification

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United States of America Patent

PATENT NO 8862770
SERIAL NO

10704041

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Abstract

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A method and apparatus for tracking packets in a processor architecture verification system are disclosed herein. An embodiment of the method comprises identifying a completion event associated with the transfer of a packet across a point to point link network of a virtual bus interface; creating an identification for the packet; and storing data associated with the packet in a database, the data being indexable by way of the identification.

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Patent Owner(s)

  • HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Maly, John Warren LaPorte, US 24 193
Smith, Zachary Steven Fort Collins, US 24 173

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