Efficient support of multiple page size segments
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United States of America Patent
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Oct 14, 2014
Issued Date -
N/A
app pub date -
May 7, 2010
filing date -
May 7, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus, system, and method are disclosed for improved support of MPS segments in a microprocessor. The virtual address is used to generate possible TLB index values for each of the supported page sizes of the MPS segment associated with the virtual address. The possible TLB index values may be a hash generated using the virtual address and one of the supported page sizes. The TLB is searched for actual TLB index values that match the possible TLB index values calculated using the different supported page sizes. TLB entries associated with those actual TLB index values are checked to determine whether any TLB entry is associated with the virtual address. If no match is found, the real address is retrieved from the PT. The actual page size in the PT is used to generate an actual TLB index value for the virtual address and the TLB entry is inserted into the TLB.
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