Manufacturing method of a semiconductor device and method for creating a layout thereof

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United States of America Patent

PATENT NO 8865583
SERIAL NO

13665803

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Abstract

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A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

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Patent Owner(s)

  • TOSHIBA MEMORY CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kodama, Chikaaki Yokohama, JP 51 387
Yanagidaira, Kosuke Fujisawa, JP 62 519

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