Current-limiting layer and a current-reducing layer in a memory device

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United States of America Patent

PATENT NO 8866121
APP PUB NO 20130026438A1
SERIAL NO

13399530

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Abstract

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A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime.

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Patent Owner(s)

  • SANDISK TECHNOLOGIES LLC;KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chiang, Tony P Campbell, US 208 9948
Hashim, Imran Saratoga, US 125 2654
Wang, Yun San Jose, US 444 6534

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