Memory devices, memory device constructions, constructions, memory device forming methods, current conducting devices, and memory cell programming methods
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United States of America Patent
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Oct 21, 2014
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N/A
app pub date -
Nov 9, 2011
filing date -
May 22, 2008
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Abstract
Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
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