Semiconductor storage device
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United States of America Patent
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Oct 28, 2014
Grant Date -
Sep 18, 2014
app pub date -
Sep 3, 2013
filing date -
Mar 13, 2013
priority date (Note) -
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Abstract
According to one embodiment, a semiconductor storage device includes multiple memory cells that include a variable resistance element and a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured so that, during the set operation in which the variable resistance element is changed to the set state, a set voltage of a first polarity is applied to the select memory cell. The control circuit is configured so that, during the reset operation in which the variable resistance elements are changed to the reset state, and a cancel voltage of the first polarity is applied to an unselected memory cell to which voltage that is less than the reset voltage was applied. The voltage value and the voltage application time of the set voltage and the voltage value and the voltage application time of the cancel voltage have a set relationship.
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