Common doped region with separate gate control for a logic compatible non-volatile memory cell
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 28, 2014
Issued Date -
N/A
app pub date -
Oct 28, 2011
filing date -
Oct 28, 2011
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and located laterally from the floating gate. In the array, first bit lines are oriented in a first direction, wherein a first bit line is coupled to drain regions of transistors that are arranged in a column. The array includes second bit lines also oriented in the first direction, wherein a second bit line is coupled to source regions of transistors that are arranged in a column. The array also includes word lines oriented in a second direction, wherein each word line is coupled to control gates of coupling capacitors that are arranged in a row.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully