Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
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United States of America Patent
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Nov 11, 2014
Issued Date -
N/A
app pub date -
Oct 14, 2013
filing date -
Aug 30, 2006
priority date (Note) -
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Abstract
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
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