Semiconductor memory device including a stacked gate having a charge storage layer and a control gate, and method of manufacturing the same
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United States of America Patent
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Nov 11, 2014
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app pub date -
Apr 22, 2011
filing date -
Nov 17, 2006
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Abstract
A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.
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