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Abstract

A digital signal processing (DSP) apparatus can be used to process a serial stream of digital signal samples of a plurality of “n” number of different signals. The DSP apparatus can include a DSP module configured to perform a DSP algorithm on digital signal samples of the signals. The DSP apparatus can have a delay memory with an “n” number of memory cells that each corresponding to one of the signals. The delay memory can also have a digital signal sample input connected to said initial input of said DSP module, a signal-number-in input, a signal-number-out input, and a digital signal sample output connected to said delay input of said DSP module. The delay memory can be configured to store a digital signal sample at the digital signal sample input in a memory cells identified by a signal identifier at said signal-number-in input. The delay memory can also be configured to output at the digital signal sample output a digital signal sample stored in a memory cells identified by a signal identifier at the signal-number-out input.

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First Claim