Mechanisms to accelerate transactions using buffered stores

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United States of America Patent

PATENT NO 8886894
SERIAL NO

13658264

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Abstract

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In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Adl-Tabatabai, Ali-Reza San Jose, US 134 4421
Bassin, Vadim Raanana, IL 20 891
Callahan, David Seattle, US 29 926
Gray, Jan Belluvue, US 49 1852
Ni, Yang Sunnyvale, US 54 480
Saha, Bratin Santa Clara, US 90 3753
Sheaffer, Gad Haifa, IL 66 1996

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