Managing errors in a DRAM by weak cell encoding
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United States of America Patent
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Nov 11, 2014
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app pub date -
Dec 11, 2012
filing date -
Dec 11, 2012
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Abstract
This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.
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