Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers

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United States of America Patent

PATENT NO 8887174
SERIAL NO

13191317

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Abstract

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A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bigbee, Bryant E Scottsdale, US 27 665
Chinya, Gautham N Hillsboro, US 41 799
Diep, Trung A San Jose, US 11 184
Hankins, Richard A San Jose, US 21 514
Kaushik, Shivnandan D Portland, US 38 1362
Patel, Baiju V Portland, US 84 1805
Petersen, Paul M Champaign, US 37 747
Rakvic, Ryan N Palo Alto, US 10 207
Sethi, Prashant Folsom, US 88 1545
Shah, Sanjiv M Champaign, US 17 403
Shen, John P San Jose, US 51 1141
Wang, Hong Fremont, US 1090 12499
Zou, Xiang Beaverton, US 105 1806

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