Methods and circuits for reducing clock jitter

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United States of America Patent

PATENT NO 8890580
SERIAL NO

13878351

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Abstract

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A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

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Patent Owner(s)

  • RAMBUS INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ren, Jihong Sunnyvale, US 46 782
Stone, Teva Chapel Hill, US 2 13
Zerbe, Jared Woodside, US 34 914

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