High noise immunity with latch-up free ESD clamp
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United States of America Patent
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Nov 18, 2014
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app pub date -
Dec 11, 2012
filing date -
Dec 11, 2012
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Abstract
A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.
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