Method of co-integration of strained-Si and relaxed Si or strained SiGe FETs on insulator with planar and non-planar architectures

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United States of America Patent

PATENT NO 8895381
SERIAL NO

13967994

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A method of forming a semiconductor device that includes providing a substrate including a biaxial strained semiconductor layer that is present directly on a dielectric layer, and patterning the biaxial strained semiconductor layer to provide a first conductivity region of a laterally relaxed semiconductor portion and a second conductivity region of a biaxial strained semiconductor portion, wherein the laterally relaxed semiconductor portion is present over an undercut region in the dielectric layer.

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  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheng, Kangguo Schenectady, US 3073 29791
Doris, Bruce B Slingerlands, US 796 13250
Hashemi, Pouya White Plains, US 600 4483
Khakifirooz, Ali Mountain View, US 842 11906
Reznicek, Alexander Troy, US 1408 11211

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