Implementing enhanced power supply distribution and decoupling utilizing TSV exclusion zone
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United States of America Patent
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Nov 25, 2014
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app pub date -
Dec 5, 2012
filing date -
Dec 5, 2012
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Abstract
Methods and structures implement enhanced power supply distribution and decoupling utilizing Through-Silicon-Via (TSV) exclusion zone areas for contacting one or more metal wiring layers on a semiconductor chip. A first wiring level in the TSV exclusion zone area includes a first wiring shape having a first hole of a first diameter. A dielectric includes second hole of a second diameter larger than the first diameter is provided above the first wiring level concentric with the first hole. A via hole extends through the first and second holes and an etch is performed to expose a top surface portion of the first wiring shape. A thin oxide is grown over the entire bore of the hole; an anisotropic etch is provided to remove horizontal portions of the thin oxide, exposing wiring shapes. The via hole is filled with a selected material to make TSV electrical connection to the exposed wiring shape.
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