Method for forming staircase word lines in a 3D non-volatile memory having vertical bit lines
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United States of America Patent
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Nov 25, 2014
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app pub date -
Mar 15, 2013
filing date -
Jun 15, 2012
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Abstract
A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate. It has vertical local bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. Methods of forming a slab of multi-plane memory with staircase word lines include processes with one masking and with two maskings for forming each plane.
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