Tin doped III-V material contacts
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United States of America Patent
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Nov 25, 2014
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app pub date -
Nov 26, 2012
filing date -
Dec 20, 2011
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Abstract
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures.
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- 15 United States
- 10 France
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- 5 Korea
- 2 Other
Patent Owner(s)
- INTEL CORPORATION
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Glass, Glenn A | Beaverton, US | 178 | 4407 |
Jackson, Michael J | Portland, US | 14 | 209 |
Kennel, Harold W | Portland, US | 60 | 223 |
Murthy, Anand S | Portland, US | 308 | 5577 |
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