Scheduling workloads based on cache asymmetry
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 25, 2014
Issued Date -
N/A
app pub date -
Mar 8, 2011
filing date -
Mar 8, 2011
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully