Integrated circuit including multiple memory devices
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United States of America Patent
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Nov 25, 2014
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N/A
app pub date -
Jul 23, 2007
filing date -
Jul 23, 2007
priority date (Note) -
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Abstract
An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal.
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