Memory address translation
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United States of America Patent
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Nov 25, 2014
Issued Date -
N/A
app pub date -
Apr 9, 2013
filing date -
Jan 6, 2011
priority date (Note) -
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Abstract
The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
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