Three-dimensional NAND memory with adaptive erase
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United States of America Patent
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Dec 2, 2014
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app pub date -
May 21, 2014
filing date -
Oct 2, 2013
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Abstract
Erasing memory cells in certain 3-D NAND charge-storage memory arrays is achieved by rapidly charging vertical conductors using Gate Induced Drain Leakage (GIDL) current generated in select transistors. When bit line voltage drops below its nominal value, select line voltage is controlled to maintain a constant voltage difference between bit line voltage and select line voltage thus maintaining a gate-drain voltage difference in select transistors that provides sufficient GIDL current for erase.
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