Method and apparatus for saving power by efficiently disabling ways for a set-associative cache

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United States of America Patent

PATENT NO 8904112
SERIAL NO

13843885

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Abstract

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A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Combs, Jonathan Austin, US 19 78
Huang, Andrew Austin, US 16 210
Licht, Martin Round Rock, US 14 79

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