Structure for stacked CMOS circuits
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United States of America Patent
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Dec 2, 2014
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Mar 26, 2013
filing date -
Mar 26, 2013
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Abstract
An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a plurality of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output.
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