Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel
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United States of America Patent
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Dec 9, 2014
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app pub date -
Jun 12, 2012
filing date -
Jun 12, 2012
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Abstract
A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.
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