Deferred page clearing in a multiprocessor computer system

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United States of America Patent

PATENT NO 8918601
SERIAL NO

12636819

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Abstract

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Processing within a multiprocessor computer system is facilitated by: logically clearing a data page by setting, in association with invalidate page table entry or set storage key processing, a page initialize bit for the data page to a clear data value without physically clearing data from the data page; and subsequent to the setting of the page initialize bit, physically clearing data from the page in central storage responsive to a first access to the page with the page initialize bit set to the clear data value, thereby minimizing overall time required to both clear and subsequently access cleared page data. Setting of the page initialize bit may include setting a line clear bit for each page line to the clear data value, and allocating a state machine to clear each line responsive to the line being first accessed with the its line clear bit set.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Woffinden, Gary A Overland Park, US 22 636

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