High-k transistors with low threshold voltage

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United States of America Patent

PATENT NO 8927409
APP PUB NO 20140038403A1
SERIAL NO

14046218

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Abstract

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An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Frank, Martin M Dobbs Ferry, US 125 1460

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