Self-aligned patterning technique for semiconductor device features
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United States of America Patent
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Jan 6, 2015
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app pub date -
Jun 28, 2013
filing date -
Jun 28, 2013
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Abstract
A method for fabricating a semiconductor device utilizing a plurality of masks and spacers. The method includes forming parallel first trenches in a substrate using a first lithographic process. The substrate includes sidewalls adjacent to the parallel first trenches. Forming first spacers adjacent to the sidewalls. Removing the sidewalls, which in part includes using a second lithographic process. Forming second spacers adjacent to the first spacers, resulting in spacer ridges. Etching portions of the substrate between the spacer ridges resulting in second trenches.
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