Complementary SOI lateral bipolar for SRAM in a CMOS platform
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United States of America Patent
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Jan 6, 2015
Grant Date -
Jun 5, 2014
app pub date -
Dec 2, 2012
filing date -
Dec 2, 2012
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Abstract
A memory array that includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.
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