Managing in-line store throughput reduction
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United States of America Patent
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Jan 6, 2015
Grant Date -
Mar 28, 2013
app pub date -
Nov 20, 2012
filing date -
Jun 22, 2010
priority date (Note) -
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Abstract
Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.
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