Reducing read latency using a pool of processing cores

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United States of America Patent

PATENT NO 8930633
SERIAL NO

13523605

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Abstract

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In a read processing storage system, using a pool of CPU cores, the CPU cores are assigned to process either write operations, read operations, and read and write operations, that are scheduled for processing. A maximum number of the CPU cores are set for processing only the read operations, thereby lowering a read latency. A minimal number of the CPU cores are allocated for processing the write operations, thereby increasing write latency. Upon reaching a throughput limit for the write operations that causes the minimal number of the plurality of CPU cores to reach a busy status, the minimal number of the plurality of CPU cores for processing the write operations is increased.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amit, Jonathan Omer, IL 120 1288
Lidor, Amir Binyamina, IL 10 469
Marenkov, Sergey Yehud, IL 56 714
Raikhman, Rostislav Rishon-leZion, IL 15 512

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