Logical address offset in response to detecting a memory formatting operation

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United States of America Patent

PATENT NO 8930671
SERIAL NO

14184876

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Abstract

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The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.

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Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Asnaashari, Mehdi Danville, US 119 2353
Benson, William E San Mateo, US 11 142

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