Load page table entry address instruction execution based on an address translation format control field
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United States of America Patent
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Jan 6, 2015
Issued Date -
N/A
app pub date -
Oct 29, 2013
filing date -
Jan 11, 2008
priority date (Note) -
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Abstract
What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.
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