Clock signals for dynamic reconfiguration of communication link bundles
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 6, 2015
Issued Date -
N/A
app pub date -
Dec 16, 2008
filing date -
Dec 16, 2008
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully