Validating cache coherency protocol within a processor
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United States of America Patent
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Jan 6, 2015
Grant Date -
Jun 19, 2014
app pub date -
Dec 17, 2012
filing date -
Dec 17, 2012
priority date (Note) -
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Abstract
A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.
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