Complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier
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United States of America Patent
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Jan 13, 2015
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app pub date -
Jan 23, 2013
filing date -
Jan 23, 2013
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Abstract
A complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier is described. In one embodiment, the DRAM cell includes an n-type field-effect transistor (NFET), a p-type field-effect transistor (PFET), and a storage capacitor accessed through both the NFET and the PFET. A pair of bit lines is coupled to the DRAM cell. A sense amplifier with a single-ended read path reads data in the DRAM cell through only one of the bit lines and a data-dependent write-back path writes back data to the DRAM cell through either one of the bit lines. The bit line used by the sense amplifier to write back the data to the DRAM cell depends on the logical value of the data.
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