Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
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United States of America Patent
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Jan 20, 2015
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Feb 20, 2014
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Mar 29, 2007
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Abstract
A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
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