Data packet arithmetic logic devices and methods
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United States of America Patent
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Jan 20, 2015
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N/A
app pub date -
Jun 25, 2013
filing date -
Jun 23, 2003
priority date (Note) -
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Abstract
New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.
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