System and method to implement a matrix multiply unit of a broadband processor
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United States of America Patent
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Jan 27, 2015
Grant Date -
Aug 23, 2012
app pub date -
May 2, 2012
filing date -
Sep 4, 2001
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Abstract
A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
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